Special Sessions
RISC-V and Open hardware: research, training and innovation towards Open-source Hw/Sw
Special Session Organizers:
Francesc Moll, Universitat Politècnica de Catalunya, Spain
Lluís Terés, IMB-CNM (CSIC), Spain
Both organizers are acting on behalf of Red-RISCV, a Spanish research network collecting members from 14 different research and academic institutions, as well as other groups interested on being associated members, and more than 25 companies aiming to contribute and follow-up the network evolution.
Summary
The RISC-V ISA was born in 2010 at UC Berkeley aiming not just to create a new RISC machine, but an open, advanced, refined and modular instruction set to address the open hardware challenges from the point of view of processor development. In 2016 the RISC-V Foundation came up to guide the open ISA standard independent evolution. Right now, thousands of worldwide members from industry and academia are part of the RISC-V Foundation ecosystem and many hardware implementations of RISC-V ISA have been made available as open source code ready for its physical materialization either in FPGA or in SoC, as well as components at chip level ready for systems development.
Mirroring the software evolution in terms of open source during the last twenty years, it seems clear that open-ISA RISC-V is an excellent opportunity to address open-source hardware for several reasons:
Mirroring the software evolution in terms of open source during the last twenty years, it seems clear that open-ISA RISC-V is an excellent opportunity to address open-source hardware for several reasons:
- We must emulate in the hardware world the effect of Linux into software open source.
- Democratize processor development by reducing third party or country dependencies facilitating and opening market competition; thus, reducing the current oligopoly of a few companies.
- Reducing costs by avoiding royalties for the ISA itself and having many different RISC-V providers to choose the best cost-performance solution for each application.
- Although RISC-V does not yet have the large infrastructures of their market competitors (Intel, ARM, AMD), it has very large expectations and interest from both industry and academia-research point of view.
- Big opportunity for the scientific community to work together and develop such an open-hardware ecosystem to address, not only RISC-V processor-based developments, but any open SoC-hardware.
- The EU Chips Act is betting on open architectures such as RISC-V for its future processors, especially since UK and ARM are no longer part of the European Union, as well as due to semiconductors shortage and related technological sovereignty strategies.
- We have the chance to get involved from the early stages into this new wave of open hardware around RISC-V and beyond it.
This special session aims to open the discussions around open hardware in general including methodologies, specific cases, training, sharing/licensing strategies and any other related topic on this wide domain in order to move towards the open hardware ecosystem. Thus, we expect your contributions on any related topic to have the right picture of our community in this domain.
Radiofrequency circuit designs based on two-dimensional devices
Special Session Organizers:
Aníbal Pacheco-Sánchez, Universitat Autònoma de Barcelona
Summary
Two-dimensional (2D) devices are based on active channels with layered materials such as graphene (G), transition metal dichalcogenides or black phosphorus. In recent years, proof-of-concept 2D analog/RF devices and applications have been successfully demonstrated. An accurate compact device modeling and systematic circuit design techniques promise to boost the performance of 2D applications towards the development of analog/RF integrated circuits, especially in heterogeneous integrated circuits with silicon CMOS as a front-end-of-line and 2D devices as the back-end-of-line. Technology groups are doing an important effort nowadays in order to provide large scale production of emerging technologies, e.g., by creating ambitious pilot lines. Hence, it is an adequate opportunity for device engineers and circuit designers to join efforts in order to complete a collaborative research framework all electronics technology requires to be successful. This session is intended to provide a perspective of the opportunity niches and challenges ahead to scale up these emerging devices to higher Technology Readiness Levels while drawing a collaborative scenario among manufacturers, device modeling engineers and integrated circuit designers.
Digital Signal Processing modules and architectures for 5G and 6G mobile networks
Special Session Organizers:
Juan Antonio López Martín - Universidad Politécnica de Madrid, Spain
Summary
Approximately every ten years a new generation of mobile networks is defined. Modern 5G systems have evolved, and now they continue under the umbrella of “5G Advanced”. 6G
networks are envisaged to evolve remarkably from 5G. They are expected to support real-time human/cyber/physical system interactions, integrate natively AI mechanisms, pursue global coverage in space/air/ground/water, and integrate communications/sensing/computing for ubiquitous intelligence. 6G mobile services aim to achieve higher data rates, higher reliability, ultra-low latency, higher mobility, massive connections, ultra-high positioning accuracy, more intelligence, more security, and better substitutability than currently defined networks.
The 6G architecture is expected to support many new use cases, while supporting existing ones in an optimal manner. To address such requirements, the 6G architecture is expected to evolve in six key areas: Flexibility, Specialization, Robustness and security, Cloud platform, Programmability, Simplification and Sustainability. Six key technologies are expected to play an essential role in 6G, including new spectrum bands and technologies, Artificial Intelligence (AI) and Machine Learning (ML) techniques, network-as-a-sensor, extreme networking with ultra-low latency, cognitive automated and specialized architecture, as well as new concepts to assure security and privacy.
The 6G communication spectrum will mainly use the THz band. The waves will have a narrow beam, and the data rates will be close to 100 Gbps. Some additional parameters that need to be investigated include: low-complexity, low-power hardware circuits, channel and noise modeling, energy efficient modulation schemes, low density channel coding, ultra massive multiple-input and multiple-output (MIMO) systems, and powerful synchronization schemes.
Advanced memristive circuits and systems (cancelled due to shortage of papers)
Special Session Organizers:
Antonio Rubio, Universitat Politècnica de Catalunya, Spain
Juan Bautista Roldán, Universidad de Granada, Spain
Marisa López Vallejo, Universidad Politécnica de Madrid, Spain
Summary
Since the fabrication of the first physical memristor in 2008 at HP Labs a lot of interest has been attracted to this area of research. Numerous groups have devoted important efforts to the fabrication, modeling, simulation, circuit design, and development of system applications based on memristive devices. There are many applications of memristive devices: non-volatile memories, neural networks, in-memory computing, cryptography, etc. However, there is still room for improvement since memristors are well known for their variability and highly non-linear behavior. Proof of this is the set of interesting research pieces we present in this session that we have collected here from different research points of view, from the device to the application level.