Keynote presentations
Title: X-HEEP: A RISC-V Open-Source, Configurable, and Extendible Platform for Heterogeneous Ultra-Low-Power Edge-Computing Devices
Davide Schiavone: Embedded Systems Laboratory (ESL) at the EPF Lausanne and Director of Engineering at the OpenHW Group
Abstract
After introducing the state of the art of open-source hardware/software and its importance and impact for growing all together in an open/collaborative way, we will introduce the platform X-HEEP (eXtendable Heterogeneous Energy-Efficient Platform).
X-HEEP is an open-source, configurable, and extensible single-core RISC-V microcontroller developed at the Embedded Systems Laboratory (ESL) of EPFL for edge-computing heterogeneous platforms. It is built on top of existing, mature open-source IPs from the OpenHW Group, the PULP team from ETH Zurich and the University of Bologna, and the lowRISC OpenTitan project and extended with custom blocks and logic to provide a system that can be easily extended via the X-HEEP interface with different accelerators, ranging from near/in-memory computing blocks, multicore systems, CGRAs, etc.
In this talk, we will show how X-HEEP can be configured to meet a wide range of requirements, how it can be extended with accelerators, and how it is used as a research platform for fast prototyping. We will show the results of our first prototype in TSMC65LP, where we used X-HEEP next to our CGRA, showing how X-HEEP and its interface can be efficiently exploited to build energy-efficient heterogeneous platforms.
Speaker bio
Davide Schiavone is a PostDoc at the Embedded Systems Laboratory (ESL) at the EPF Lausanne and Director of Engineering at the OpenHW Group. He obtained the Ph.D. title at the Integrated Systems Laboratory of ETH Zurich in the Digital Systems group in 2020. His main activities involve computer architecture designs based on RISC-V CPUs, including accelerators based on custom instructions, in/near-memory platforms, embedded FPGAs, etc., for ultra-low-power, energy-efficient smart wearable systems, and human-machine interfaces. His main experiences include designing two RISC-V open-source IPs and implementing RISC-V-based SoCs for edge-computing applications in the milliWatt range. He is also delivering training workshops to companies and universities as a freelancer.
